1. Field of the Invention
The present invention relates to self-refresh circuits in semiconductor memory devices, and more particularly, to a system and method for reducing self-refresh current requirements.
2. Background Information
In the portable consumer electronics industry, recent advancements in microprocessor speeds and memory storage capabilities have resulted in a new generation of portable devices with significantly improved functionality. Along with additional features, portable electronic devices are continually being designed to operate more efficiently to draw less electrical current, and hence require less battery power. Such electronic devices (such as laptops, digital cameras, digital cellular telephones, personal digital assistants) are now capable of operating for longer periods of time before requiring battery replacement or recharge, which can be useful to consumers and are less expensive to operate.
Many portable electronic devices include dynamic random access memory (“DRAM”) for temporary, or “volatile” (i.e., constant power required) data storage. A conventional DRAM is comprised of a plurality of memory cells within arrays of word lines and bit lines, arranged in a grid. As seen in FIG. 1, a single memory cell consists generally of a single transistor 10 and a single capacitor 11. The cell is accessed by activating a combination of a particular word line and bit line.
To write a data bit into a cell, an appropriate voltage is applied to the word line, which turns on the transistor 10, along with each other transistor on the word line. A high voltage (typically near 1.5V or 2V) or low voltage (typically near 0V) is then presented at the bit line to charge the capacitor 11 to a logic high or logic low value. When the voltage is removed from the word line, the charge on the capacitor remains to store a bit of information. Typically, an entire word is written into or read from a DRAM array by applying the voltage to the word line and an imposing or sensing voltage on each of the bit lines.
The charge levels that are stored in the capacitors of the DRAM array are affected by leakage currents, which causes the stored voltage values to dissipate over time. To maintain the accuracy of the data being stored in the capacitors, each cell of the DRAM periodically must be refreshed. This typically is accomplished by reading the data through a sense amplifier. This read operation automatically refreshes the cell signal because the memory cell is connected to the bitline during the voltage sensing and amplification process such that full signal levels are restored. Refresh operations were typically administered by commands from an external memory controller/processor, which intercedes during “stand-by” or “waiting” periods between read/write operations. More recently, DRAMs have been configured within self-refresh circuitry internal to the DRAM for carrying out refresh operations upon receiving a refresh command from the controller/processor (and selecting automatically the right cells to be refreshed).
The frequency by which memory periodically must be refreshed depends upon several factors, but it is typically refreshed at least every few hundred milliseconds (this is done in “small portions,” for example, 7.8 μs each to restore the whole DRAM in 64 ms, i.e., 8 k refresh events are required . . . 8 k×7.8 ms=64 ms). Refresh rates for particular DRAM arrays are typically established by the manufacturer, based upon a worst-case high temperature condition. Generally, the overall relationship between temperature and refresh rates for DRAM arrays exhibit a positive slope, such that power consumption rises along with DRAM temperature. Since memory cells tend to vary slightly during manufacturing, the refresh rate is determined according to the fastest decaying bit of information in the DRAM. In other words, the refresh rate is determined according to the lowest-common denominator of performance, such that refresh operations successfully maintain the stored memory information in each memory cell. This can be performed by testing all of the cells of a manufactured DRAM to determine the decay time for each cell.
Refresh operations in a self-refresh circuit may be performed by utilizing an internal counter to sequentially address the cells, such that each cell is refreshed within a certain period of time. FIG. 2 is a known configuration of a DRAM with self-refresh capabilities. In this configuration, signal generator 20 provides a refresh clock signal to a refresh control circuit 22. As shown in FIG. 2, the refresh circuit is connected only to the row decoder. The rows in row decoder 24 are addressed such that each of the rows is addressed within the maximum refresh time of the memory device after a certain number of refreshments.
Since refresh operations require continuous charging and discharging of bitlines, it is power-consuming and the refresh process detracts from DRAM operating performance. Accordingly, several techniques have been developed to reduce the power required to refresh DRAMs. For example, one such technique is to slow down the refresh rate when the DRAM is operating at lower temperatures, when the decay time is longer such that a high refresh rate is not necessary. This can be done by slowing down the timer itself, or by designing refresh logic associated with the timer to only refresh only a fraction of the time when the DRAM is operating at a low temperature. Another technique is to design DRAMs such that the DRAM can be configured to operate at a selected refresh rate, depending upon the anticipated use. This can be accomplished by incorporating a fuse within the refresh circuitry, and then blowing the fuse to change the DRAM's refresh rate.
To further improve memory performance and reduce power consumption associated with DRAMs, semiconductor designers continually seek to improve refresh operations and decrease refresh rates. In view of the foregoing, it can be appreciated that a substantial need exists for a method and system for reducing self refresh current requirements in a DRAM without negatively affecting other performance characteristics of the semiconductor memory.